1. Field of the Invention
The present invention relates to a scan circuit for use in a peripheral driving circuit of a liquid crystal display, a close contact type image sensor, a liquid crystal shutter and the like.
2. Description of Related Art
For the purpose of manufacturing a liquid crystal display, a close contact type image sensor, a liquid crystal shutter, and fluorescent display tube in a small size, at a low cost and with high reliability, there is a technique of forming a thin film driving circuit integral with these devices. This is based on a conception in which if a peripheral driving circuit is provided on the same substrate as that on which pixel electrodes are provided, it is possible to greatly reduce the number of connection terminals and the number of external driving ICs (integrated circuits), and therefore, it is possible to solve a reliability problem caused by restriction in a bonding process for a large area and in a high density.
A scan circuit composed of a shift register and an output buffer, is used as a vertical driving circuit in an active matrix liquid crystal display, or as a circuit for scanning a sample hold switch in a horizontal driving circuit, and therefore, constitutes an important element in the thin film driving circuit.
One example of the shift register used in such a scan circuit is described in "Fundamental of MOS Integrated Circuit", Pages 101-102, 1992, Kindaikagakusha (Japan). Referring to FIG. 1, there is illustrated a circuit construction of an essential circuit described in this book, but only (2N-1)th and (2N)th stages of the scan circuit are extracted and shown, although the scan circuit is formed by cascading stages of the predetermined number dependent upon the size of a display circuit to be driven.
The shown circuit includes shift registers 20 and 21 for transferring a pulse signal in a delayed timing in synchronism with a clock signal, and output buffers 30 and 31. The shown shift register 20 is formed by cascading two dual-phase-clock controlled CMOS inverters 201 and 202 which are respectively controlled by two clock signals .phi. and .phi. complementary to each other. Similarly, the shift register 21 is formed of two cascaded clocked CMOS inverters 211 and 212.
FIG. 2 shows a construction of a dual-phase-clock controlled CMOS inverter circuit 201. The dual-phase-clock controlled CMOS inverter circuit 201 is called a "clocked CMOS inverter", and is formed by cascading P-channel insulated-gate electric field transistors (called "PMOS transistor" hereinafter) P3 and P4 and N-channel insulated-gate electric field transistors (called "NMOS transistor" hereinafter) N3 and N4 between a voltage supply voltage Vdd and ground GND.
When the clock signal .phi. is a high level and the clock signal .phi. is at a low level, the clocked CMOS inverter outputs an inverted signal of an input signal. To the contrary, when the clock signal .phi. is at a low level and the clock signal .phi. is at a high level, an output of the clocked CMOS inverter becomes a high impedance.
Referring to FIG. 3 which is a timing chart illustrating an operation of the conventional scan circuit shown in FIG. 1, this conventional scan circuit operates in such a manner that if a pulse signal having a pulse width T (where T is one period of clock signal) is applied as an input signal at the moment the clock signal .phi. rises from a low level to a high level, a pulse signal is outputted from a node A at the moment the clock .phi. rises up. This signal is inputted to the next stage of shift register 21, so that a pulse signal is outputted from a node B at a rising-up timing of the clock .phi. delayed from the signal of the node A by the period T.
As a result, the pulse signals having the pulse width T are outputted as the (2N-1)th stage and the (2N)th stage (where "N" is positive integer) through the output buffer circuits 30 and 31, respectively.
With a tendency towards large area, long length and high resolution in the liquid display, the close contact image sensor and the like, a scan circuit of 1000 to 6000 stages has become required in a peripheral driving circuit. In the case that the conventional scan circuit shown in FIG. 1 is incorporated in these devices, a delay of the clock signal caused by an increased load capacitance of clock signal lines has become a problem.
For example, the load capacitance of the clock signal lines in the 2000-stage scan circuit in 50 .mu.m pitch standard reaches 500 pF, and the clock signal delay reaches 220 nsec. About 80% of this load capacitance is due to a capacitance in a crossing part of two clock signal lines, and the remaining 20% is a gate capacitance of MOS transistors and an internal wiring capacitance of a circuit.
Therefore, it is difficult to write and read a signal at a speed higher than 4 MHz in the case of using the conventional scan circuit. The circuit malfunctions due to influence of the clock skew. The conventional scan circuit cannot meet the requirements of the liquid crystal display and the close contact image sensor of high speed and high resolution which are expected to be increasingly widely used.